Search for: All records

A wafer-scale CMOS-compatible process for heterogeneous integration of III-V epitaxial material onto silicon for photonic device fabrication is presented. Transfer of AlGaAs-GaAs Vertical-Cavity Surface-Emitting Laser (VCSEL) epitaxial material onto silicon using a carrier wafer process and metallic bonding is used to form III-V islands which are subsequently processed into VCSELs. The transfer process begins with the bonding of III-V wafer pieces epitaxy-down on a carrier wafer using a temporary bonding material. Following substrate removal, precisely-located islands of material are formed using photolithography and dry etching. These islands are bonded onto a silicon host wafer using a thin-film non-gold metal bonding process and the transfer wafer is removed. Following the bonding of the epitaxial islands onto the silicon wafer, standard processing methods are used to form VCSELs with non-gold contacts. The removal of the GaAs substrate prior to bonding provides an improved thermal pathway which leads to a reduction in wavelength shift with output power under continuous-wave (CW) excitation. Unlike prior work in which fullyfabricated VCSELs are flip-chip bonded to silicon, all photonic device processing takes place after the epitaxial transfer process. The electrical and optical performance of heterogeneously integrated 850nm GaAs VCSELs on silicon is compared to their as-grown counterparts. The demonstrated method creates the potential for the integration of III-V photonic devices with silicon CMOS, including CMOS imaging arrays. Such devices could have use in applications ranging from 3D imaging to LiDAR. 

Sensory IoT (Internet of Things) networks are widely applied and studied in recent years and have demonstrated their unique benefits in various areas. In this paper, we bring the sensor network to an application scenario that has rarely been studied - the academic cleanrooms. We design SENSELET++, a low-cost IoT sensing platform that can collect, manage and analyze a large amount of sensory data from heterogeneous sensors. Furthermore, we design a novel hybrid anomaly detection framework which can detect both time-critical and complex non-critical anomalies. We validate SENSELET++ through the deployment of the sensing platform in a lithography cleanroom. Our results show the scalability, flexibility, and reliability properties of the system design. Also, using real-world sensory data collected by SENSELET++, our system can analyze data streams in real-time and detect shape and trend anomalies with a 91% true positive rate. 

Enhancing the functionality of silicon through the integration of other materials such as III-V semiconductors has been recognized as a path to overcoming limitations imposed by characteristics fundamental to silicon's material physics while still capitalizing on properties that have enabled the success of the global integrated circuit industry [1]–[2][3]. High-speed electronic devices, devices with high breakdown voltages, light emitting/detecting devices, and devices for photon control can all be integrated with conventional CMOS to perform specialized electronic or photonic functions if suitable methods for forming such heterogeneously integrated regions are available that provide high yield and are compatible with fabrication processes that occur subsequent to the heterogeneous integration process. Technical challenges include lattice mismatch, thermal expansion coefficient differences, having the capability to form low-resistance electrical contacts using materials that are compatible with CMOS, more generally managing cross-contamination in tools used for front-end-of-line processing after III-V regions are established on the silicon wafers, and thermal management for the heterogeneously integrated devices or circuits. These together create formidable obstacles, but there is also the obstacle of defining a business case for creating hybrid wafer fabs given the applications that would be served by ICs with enhanced functionality. Bringing functions that are off chip onto the chip needs to be justified both technically and financially. 

We present a hybrid optical-electrical analog deep learning (DL) accelerator, the first work to use incoherent optical signals for DL workloads. Incoherent optical designs are more attractive than coherent ones as the former can be more easily realized in practice. However, a significant challenge in analog DL accelerators, where multiply-accumulate operations are dominant, is that there is no known solution to perform accumulation using incoherent optical signals. We overcome this challenge by devising a hybrid approach: accumulation is done in the electrical domain, while multiplication is performed in the optical domain. The key technology enabler of our design is the transistor laser, which performs electrical-to-optical and optical-to-electrical conversions efficiently to tightly integrate electrical and optical devices into compact circuits. As such, our design fully realizes the ultra high-speed and high-energy-efficiency advantages of analog and optical computing. Our evaluation results using the MNIST benchmark show that our design achieves 2214× and 65× improvements in latency and energy, respectively, compared to a state-of-the-art memristor-based analog design. 

An array of active photonic devices is fabricated in unison after a heterogeneous integration process first metal-eutectically bonds these distinct materials as a distribution onto a silicon host wafer. The patterning out of heterogeneous materials followed by the formation of all photonic devices allows for wide-area fine-alignment without the need for discrete die alignment or placement. The integration process is designed as a CMOS-compatible, scalable method for bringing together distinct III-V epitaxial structures and optical-waveguiding epitaxial structures, demonstrating the capabilities of forming a multi-chip layer of photonic materials. Integrated GaAs-based vertical light-emitting transistors (LET) are designed and fabricated as the active devices whose third electrical terminal provides an electrical interconnect and thermal dissipation path to the silicon host wafer. The performance of these devices as both electrical transistors and spontaneous-emission optical devices is compared to their monolithically-integrated counterparts to investigate improvements in device characteristics when integrated onto silicon. The fabrication methods are modified and optimized for thin-film transferred materials and are then extended to transistor laser (TL) fabrication. Passive waveguiding structures are designed and simulated for coupling light from the active devices, and their fabrication scheme is presented such that it can be similarly performed with transferred materials. Work toward the demonstration of integrated transistor lasers is shown to represent progress toward an electronic-photonic circuit network. The combination of heterogeneous integration with three-terminal photonic structures enables an elegant solution to both packaging and signal interconnect constraints for the implementation of photonic logic in silicon photonics systems. 

Semiconductor cleanrooms are used to fabricate devices with feature sizes that can be much smaller than a dust particle. Hence, any environmental deviations in temperature, or humidity around fabrication instruments may become the root cause of hundreds of transistors failing during the manufacturing. Furthermore, researchers work with dangerous chemicals in cleanrooms and violation of safety may lead to disastrous consequences. Therefore, we have developed an affordable, locally-controlled distributed sensing infrastructure, called SENSELET, for academic cleanrooms. It provides highly effective services for environment sensing around scientific instruments, sensory data collection and visualization, indoor localization, and instrument proximity detection for safety of researchers. 

We present a new interposer-level optical network based on direct-modulated lasers such as vertical-cavity surfaceemitting lasers (VCSELs) or transistor lasers (TLs). Our key observation is that, the physics of these lasers is such that they must transmit significantly more power (21×) than is needed by the receiver. We take advantage of this excess optical power to create a new network architecture called Rome, which splits optical signals using passive splitters to allow flexible bandwidth allocation among different transmitter and receiver pairs while imposing minimal power and design costs. Using multi-chip module GPUs (MCM-GPUs) as a case study, we thoroughly evaluate network power and performance, and show that (1) Rome is capable of efficiently scaling up MCM-GPUs with up to 1024 streaming multiprocessors, and (2) Rome outperforms various competing designs in terms of energy efficiency (by up to 4×) and performance (by up to 143%).